Delta-Sigma AD-Converters by Richard Gaggl
Author:Richard Gaggl
Language: eng
Format: epub
Publisher: Springer Berlin Heidelberg, Berlin, Heidelberg
3.3 Measurement Results
The modulator was implemented in a 0.18 μm 4-metal CMOS technology using a dual-gate-oxide process option for the switches. The linear capacitors were implemented as metal-insulator-metal (MIM) devices. The evaluation of the prototype needs to be done very carefully due to practical constraints in measurement [47]. The chip-size results in 1.9×1.9 mm2, which is relatively small for a standard CQFP-64 package resulting in bondwire length of more than 7 mm. Such long bondwires exhibit an inductance bigger than 5 nH forming a parasitic LC-tank together with the SC-input stage of the ADC. Avoiding undesirable effects involves a continuous-time pre-filter stage for signal decoupling reasons. A fully differential voltage generator is applied to the on-chip pre-filter which drives the delta-sigma ADC. The 2nd order Butterworth-filter has a −3 dB corner-frequency of 500 kHz providing an anti-aliasing filter. The on-chip references are implemented fully differentially in a feed-back configuration. The quantizer uses a separated reference circuit. The overall bias-currents and reference voltages are derived from an on-chip programmable biasing circuit including a bandgap. Figure 3.8 shows the complete layout of the test-chip. A photograph of the die is shown in Fig. 3.9. The ADC core-area results in 0.21 mm2, all required reference buffers consume additionally 0.18 mm2 of chip area. The whole signal-path is implemented fully differential. Avoiding crosstalk issues requires a separated supply for the analog and the digital part as well as the central biasing .
Fig. 3.8Layout of the 0.18 μm test-chip
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